Typically, a clock source outputs a clock signal that synchronizes the activities in large synchronous systems, such as memory arrays. The clock signal acts as both a sequence reference and as a time reference for events within the synchronous system. As a sequence reference, the clock transitions define successive instants at which system state changes occur. As a time reference, the time period between clock transitions accounts for system delays occurring between the output of the clock source and the input to a selected clocked element in the synchronous system.
Differences in the arrival of the clock signal at two or more clocked elements can result in errors in the synchronous system. Clock skew is defined as the time delay between generation of the clock signal at a clock source and arrival of the clock signal at a selected clocked element. Differences in clock skew between the clock source and different clocked elements can create errors in the synchronous system as the clocked elements are triggered at different points in time.
For example, the sum of the all the capacitance in the registers in a large CMOS device may exceed 100 pF. Driving this level of capacitance in a small time and at a high frequency can create substantial clock skew. In addition, the clock skew typically changes as the path length between the clock source and the selected clocked element varies and as the capacitance and/or resistance of the conductive path between the clock source and the clocked element varies. Thus, one clocked element having a first path length from the clock source and a second clocked element having a second path length from the clock source are subject to different clock skews. These variations in clock skew at the clocked elements of the synchronous system create inaccuracies in system synchronization.
Two main techniques are known for combating errors caused by clock skew: the use of a single large buffer for driving the clock signal, and the use of a distributed clock-tree. In the first approach, a single buffer is used to drive a global clock that feeds all elements in the synchronous system. This approach is preferred in designs having a large number of diverse modules that lack a structured routing approach. Clocked elements both near to the clock source and far from the clock source are driven by the same buffer. Accordingly, clocked elements near the clock source receive a clock signal having a different clock skew than clocked elements far from the clock source. These differences in clock skew can cause errors in synchronizing the clocked elements.
A second approach involves distributed clock trees having suitable geometry for transmitting the clock signal to the clocked elements in the synchronous system. Either the delay along each path of the clock tree can be carefully simulated and matched, although such simulations are typically inaccurate, or the distribution of the clock can be arranged so that any RC delay occurs in a safe skew direction. One distributed clock tree technique is an H-tree scheme for distributing the clock signal, as shown in FIG. 6. The illustrated H-tree scheme distributes the clock signal along branches in a tree wherein the leaves in the tree are the clocked elements of the synchronous system. H-tree schemes can be used to distribute the clock signal to regular arrays within a synchronous system such that every element in the synchronous system is the same distance from the clock generator. The H-tree scheme, however, suffers from other drawbacks. In particular, H-tree schemes have clock skews proportional to the size of the synchronous array considered, such that H-trees implemented with large synchronous arrays suffer from severe clock skew that can even extend beyond the time period of one clock cycle.
Accordingly, there is a need for a synchronous system that distributes a clock signal with reduced error caused by clock skew.